Edit: it’s freaking 4000 19-21-21 Samsung B-die
. Also, apparently there’s a second XMP at 3600 17-18-18 so you should probably just load that and forget about all the hassle 🤣🤣🤣.
Okay so there are a few issues with any 4000+ XMP kits on Ryzen. One of the main issues is similar to one of the weaknesses of DDR5. When your IMC can’t address your RAM 1:1 in terms of clock cycles, you take an instant hit because you can only do 1:2 (IMC
RAM) or 1:4 (DDR5 IMCs and super high speed DDR5).
When I used the Ballistix Max 5100s, I would often just run my daily 5000C18 because the IMC at 1250MHz and the FCLK unlinked to 1900MHz weren’t significant enough performance hits to make 5000C18 not worth using.
So now we get to the kits that you’d run at 4000-4400. At 4000Mbps you’re talking a likely result of a 1000MHz IMC (I highly doubt your 3600 will do 2000MHz on the UCLK), and FCLK will likely land between 1733-1866 (many Ryzen 3000s couldn’t do 1900 FCLK).
The only logical way to actually go about this would be to set your UCLK//MEMCLK manually to 1:1 (that’s what the setting looked like on MSI boards that I used), but it should be similar on other boards. The reason for this is that a 1000MHz IMC would be far worse than slightly lowering your current DRAM freq. Similarly, you should test 1800-1900 FCLK and see where your CPU is willing to go. As a rule you can generally max out SoC to 1.1-1.15 (I used to run 1.2), and you set VDDG IOD to 50mV below SoC (maybe try 1.15V SoC and 1.1V IOD). CCD can be set to 0.9V for your kit, and you can probably just set VDDP to 0.95V (you’d push higher for higher-bin kits but not in this scenario).
All of the above is to stabilise your theoretical max Fabric Clock (FCLK). Set RAM to XMP, but manually drop the memory clock to DDR4 3600-3800 depending on where your FCLK caps out (very much trial and error and keep an eye on HWiNFO WHEA errors). Keep UCLK//MEMCLK at 1:1 or =, and make sure your UCLK:FCLK:MEMCLK are 1:1:1. As a tip, 3800 DDR4 is 1900MHz (you might know this).
Irrespective of what your XMP timings are, you are far better off dropping the 4000Mbps to 3800Mbps to (hopefully) facilitate 1:1:1 ratio as you’ll claw back fat more performance than allowing UCLK to drop to the floor at 1000MHz, and running unlinked FCLK.
What I would personally do, is all of the above, but I’d run SoC at 1.2, IOD at 1.15, VDDP at 1.05 and CCD at 1.0. I’d load up XMP for memory training purposes, but I’d portably just check the IC of the kit, set a max DDR voltage based on the IC, and begin manually tuning the primaries and secondaries to compensate for the mandatory memory freq drop.
For instance I had a profile at 3800 13-17-17-34-1T 1:1:1 for the Ballistix 5100 kit that I would sometimes benchmark against the higher freq kit, and occasionally I’d game on it if I felt bored of the 5000C18 profile.
